1. Field of the Invention
The present invention relates to a device for controlling a data storage device, such as DRAM (dynamic random access memory) and the like, and to a method for controlling the data storage device which is connected to a CPU and the like in a data processing system.
2. Description of Related Art
DRAM is generally used as a main memory for a microprocessor or the like computer. Efforts have been made to increase the capacity of this DRAM in order to improve the performance of the entire computer systems.
In recent years, there has been increasing demand not only to increase the memory capacity, but also to increase the data transfer rate of the DRAM in accordance with increase in the speed of microprocessors. This has led to the development of various types of high speed DRAM.
Representative examples of the high-speed DRAM includes: DRAM provided with high-speed access mode called "fast page mode". DRAM provided with extended data out (EDO) page mode; DRAM provided with burst extended data out (EDO) page mode; synchronous DRAM (SDRAM); and Rambus DRAM. The SDRAM and Rambus DRAM are synchronous DRAMs, while the fast page mode DRAM, the EDO-DRAM, and the burst EDO-DRAM are asynchronous DRAMs.
Recently, SDRAM is generally used as a main memory in a high performance machine such as a server computer. The SDRAM is now being used also in other several machines of personal use such as personal computers and personal printers.
The SDRAM is a high-speed DRAM that can operate in synchronization with a clock signal supplied to a computer such as a microprocessor. There has been realized such a high-speed SDRAM that can attain a high data transfer rate of 800 megabytes per second using a 64 bit wide data bus and a clock signal at frequency of 100 MHz.
In order to attain this high-speed operation, SDRAM is provided with an internal column address counter. The column address counter is mounted on a SDRAM chip. This internal address counter is used during a transfer mode called "burst mode". When column address data is inputted, the column address counter counts up, from the inputted column address, a successive series of column addresses in synchronization with a clock signal, whereby data reading/writing operation can be executed on the successive series of addresses.
It is noted that a user can freely set burst length and CAS latency of the burst mode. The burst length is defined as the number of data to be serially inputted/outputted in synchronization with the clock signal. The CAS latency is defined as the number of clock cycles set after a column address strobe signal CAS is inputted until data is actually started being outputted. Thus, the system can be designed according to the user's desire.